ATmega128
See “Output Compare Units” on page 120. . The compare match event will also set the compare
match flag (OCFnA/B/C) which can be used to generate an output compare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-
gered) event on either the Input Capture Pin (ICPn) or on the Analog Comparator pins ( See
“Analog Comparator” on page 227. ) The Input Capture unit includes a digital filtering unit (Noise
Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined
by either the OCRnA Register, the ICRn Register, or by a set of fixed values. W hen using
OCRnA as TOP value in a P W M mode, the OCRnA Register can not be used for generating a
P W M output. However, the TOP value will in this case be double buffered allowing the TOP
value to be changed in run time. If a fixed TOP value is required, the ICRn Register can be used
as an alternative, freeing the OCRnA to be used as P W M output.
Definitions
The following definitions are used extensively throughout the document:
Table 57. Definitions
BOTTOM
MAX
TOP
The counter reaches the BOTTOM when it becomes 0x0000.
The counter reaches its MAX imum when it becomes 0xFFFF (decimal 65535).
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be one of the fixed values:
0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCRnA or ICRn
Register. The assignment is dependent of the mode of operation.
Compatibility
The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit
AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version
regarding:
?
?
?
All 16-bit Timer/Counter related I/O register address locations, including timer interrupt
registers.
Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers.
Interrupt vectors.
The following control bits have changed name, but have same functionality and register location:
?
?
?
P W Mn0 is changed to W GMn0.
P W Mn1 is changed to W GMn1.
CTCn is changed to W GMn2.
The following registers are added to the 16-bit Timer/Counter:
?
?
Timer/Counter Control Register C (TCCRnC).
Output Compare Register C, OCRnCH and OCRnCL, combined OCRnC.
The following bits are added to the 16-bit Timer/Counter Control Registers:
?
?
?
COM1C1:0 are added to TCCR1A.
FOCnA, FOCnB, and FOCnC are added in the new TCCRnC Register.
W GMn3 is added to TCCRnB.
Interrupt flag and mask bits for output compare unit C are added.
The 16-bit Timer/Counter has improvements that will affect the compatibility in some special
cases.
113
2467X–AVR–06/11
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